We seek to advance the state of the art for parallel systems. Usually, the layers of a parallel system—the compiler, run-time system, operating system, and hardware—are considered as separate entities with a rigid division of labor. This project investigates an alternative model, interweaving, in which these layers are integrated as needed to improve the performance, scalability, and efficiency of the specific parallel system.

The research involves five thrusts:

  1. Blending studies using compiler technology to achieve integration of code that would normally be found in distinct, separately compiled layers.
  2. Coherence considers hardware without memory coherence and its implications throughout the interwoven parallel system.
  3. Predictability studies the integration of hard real-time behavior into a parallel system through hardware and compiler support.
  4. Mapping considers address translation for parallel systems given hardware and compiler support.
  5. Debugging studies how to debug an interwoven system.
These investigations go hand-in-hand with the continual development of a prototype and its evaluation.








The Interweaving Project is made possible by support from the National Science Foundation via awards CCF-1533560 (Northwestern), CNS-1763743 (Northwestern), CCF-2028958 (IIT), CNS-1763612 (IIT), CNS-1730689 (IIT), CCF-1757964 (IIT), equipment donations through the Intel Parallel Computing Center at Northwestern, and generous equipment access by Intel.